1. Field of the Invention
The present invention relates to a high-speed scanning radio receiver, and, more particularly, to an automatic scanning system and method for a radio receiver.
2. Description of the Prior Art
A noise squelch circuit for detecting the presence or absence of an audio signal is used in an FM high-speed scanning radio receiver in which channels are scanned (searched) through an electronic tuning circuit employing a frequency synthesizing technique.
FIG. 1 is a block diagram showing a basic construction of the FM high-speed scanning radio receiver according to a prior art in which reference numeral 10 denotes a reception antenna, reference numeral 12 a radio receiving unit, reference numeral 14 a frequency discriminator, reference numeral 16 a noise squelch circuit, reference numeral 18 a low-frequency amplifier reference numeral 20 a speaker, reference numeral 22 a window detector, reference numeral 24 a frequency synthesizer, reference numeral 26 a CPU, and reference numeral 28 a keyboard.
In the prior art radio receiver, the noise squelch circuit 16 detects a noise level as a noise detection voltage and compares the noise detection voltage with a reference voltage V.sub.TH set by a squelch control provided therein during a channel scanning. When the noise detection voltage becomes lower than the preset reference voltage V.sub.TH as shown in FIG. 2(a), the noise squelch circuit 16 generates a squelch signal (hereinafter, referred to as an SC signal) to the CPU 26. When the CPU 26 receives the SC signal, the CPU recognizes that an audio signal has been received in a channel presently scanned and stops the channel scanning. In the radio receiver, since the response characteristic of the noise squelch circuit is not so fast, the SC signal is not generated immediately when the audio signal is received in the current channel, and thus there has been a problem in that it takes a long time to perform searching.
In order to solve the above problem, an improvement has been provided, wherein a signal (hereinafter, referred to as an SP signal) is generated by the noise squelch circuit when a decreasing trend (a portion A circled by a dotted line shown in FIG. 2(b)) is found in the noise detection voltage, and this SP signal is used together with the SC signal to detect the presence or absence of the audio signal. In other words, only when the SP signal is generated and detected in connection with a certain channel, the CPU searches for a predetermined period of time (for example 100 ms) to try to determine whether or not the SC signal regarding the channel is generated, while if no SP signal is detected, the scanning is shifted to the next channel after confirming that no SC signal is generated. Thus as a whole, a high-speed scanning can be attained.
Hereinafter, a scanning system performing the above scanning manner is referred to as a turbo scanning system. The basic idea of the turbo scanning system is disclosed in U.S. Pat. No. 5,199,109 entitled "MULTI CHANNEL SCANNING RECEIVER WITH IMPROVED SIGNAL STRENGTH DETECTION CIRCUITRY." The U.S. Patent is referred to herein.
In the prior art turbo scanning system, since a change in the noise detection voltage is monitored at the noise squelch circuit, when a change in voltage is small, there is a possibility that no SP signal is generated. FIGS. 3(a)-3(c) illustrate such a situation as above. FIG. 3(a) shows the relationship between reception bands 1, 2, 3 of channels sequentially scanned wherein the reception band 3 includes the central frequency of a signal B to be tuned by the radio receiver, FIG. 3(b) shows a change in the noise detection voltage detected in the noise squelch circuit when the reception bands are scanned in order 1, 2, and 3, and FIG. 3(c) shows a SP signal which may be generated from the noise squelch circuit in response to the noise detection voltage shown in FIG. 3(b).
As illustrated in FIG. 3(b), in the reception band 1, the noise detection voltage varies by V.sub.A from V.sub.O which is the voltage in case that there is no audio signal. Since the voltage change V.sub.A is large enough, the SP signal which is a pulse is developed at the noise squelch circuit as shown in FIG. 3(c). In the reception band 2, the noise detection voltage changes by V.sub.B from V.sub.O -V.sub.A, and then the SP signal pulse is generated again because the voltage change is also large enough. In the reception band 3, the frequency of the signal B is contained in the center thereof to which the receiver must be tuned. Since the amount of change value V.sub.C of the noise detection voltage is substantially small in comparison with V.sub.A and V.sub.B, there is generated no SP signal. When no SP signal is generated, searching will be shifted to the succeeding channel, resulting in a failure in tuning.
With reference to FIG. 4, including FIGS. 4(a) and 4(b) showing a processing flowchart to be executed at the prior art turbo scanning system in the conventional high-speed scanning radio receiver having the constitution as shown in FIG. 1, the above tuning situation will now be described in detail below.
In the turbo scanning operation, the CPU 26 controls a PLL-LOCK detection timer incorporated therein to start counting at step S1 and judges at step S2 whether or not a PLL circuit of the frequency synthesizer 24 is locked. If no PLL locking is detected and the PLL-LOCK detection timer has not timed out yet (step S3), the processing flow returns to step S2, while if the PLL locking is detected at step S2 within a predetermined time period preset at the PLL-LOCK detection timer, the CPU 26 causes a SP signal detection timer incorporated therein to start counting at step S4 and it is determined at step S5 whether or not the SP signal is detected within a SP detection waiting time period of 10 ms preset at the SP signal detection timer. If there is detected no SP signal and the SP signal detection timer has not timed out yet (step S6), the flow returns to Step S5.
If the SP signal is detected at step S5, the CPU 26 controls a SC signal detection timer incorporated therein to start counting at step S7 and the CPU judges at step S8 whether or not the SC signal is generated within a SC detection waiting time period of 100 ms preset at the SC signal detection timer. If there is detected no SC signal and the SC signal detection timer has not timed out yet (step S9), the flow returns to step S8. If the SC signal is detected at step S8, the CPU 26 detects at step S10 whether or not a window signal (hereinafter, referred to as a WD signal) from the window detector 22 is generated. If the WD signal is detected, the flow returns to step S8, and if not, the CPU supplies PLL data of the next channel to the frequency synthesizer 24 at step S11.
In addition, if the PLL-LOCK and SP detection timers are determined to have timed out respectively at steps S3 and S6, a further check, or whether or not the SC signal is generated, is performed at step S12 to make sure that no SC signal has been generated. If the SC signal has been generated, the flow proceeds to step S7 , while if not, the flow proceeds to step S11.
Although the processing flow in general has been described as above, below is given a concrete description of an operation of the CPU when the noise detection voltage changes as shown in FIG. 3(b). FIGS. 5(a)-5(c) respectively represent timing charts of PLL data sending timing, the SP signal, and the SC signal. These timing charts will also be referred to, together with the flowchart shown in FIGS. 4(a) and 4(b).
When the PLL data of a channel corresponding to the reception band 1 is sent from the CPU 26 to the frequency synthesizer 24 at step S11, the PLL-LOCK detection timer is controlled to start counting at step S1. If the PLL locking is detected at step S2, the SP signal detection timer is controlled to start counting at step S4 and the detection of the SP signal is carried out for 10 ms at step S5. Since the SP signal is generated in the reception band 1 as shown in FIG. 5(b) (and FIG. 3(c)), when the SP signal is detected, the SC signal detection timer is controlled to start counting at step S7, the detection of the SC signal is carried out for 100 ms at step S8. In this case, since there is generated no SC signal as shown in FIG. 5(c), when the SC signal detection timer times out (step S9), the PLL data of the channel corresponding to the next reception band 2 is provided to the frequency synthesizer 24 at step S11.
Accordingly, the detection of the SP signal is then carried out for 10 ms after the PLL locking is detected (steps S1-S5). Since there is also generated the SP signal in the reception band 2 as shown in FIG. 5(b) (and FIG. 3(c)), when the SP signal is detected, the SC signal detection timer is controlled to start counting at step S7, and the detection of the SC signal is performed for 100 ms (step S8). In this case, since there is generated no SC signal as shown in FIG. 5(c), when the SC signal detection timer times out (step S9), the PLL data of the channel corresponding to the reception band 3 is provided to the frequency synthesizer 24 from the CPU 26 at step S11, and the detection of the SP signal is conducted for 10 ms after the PLL locking is detected (steps S1-S5). In this case, since there is generated no SP signal as shown in FIG. 5(b) (and FIG. 3(c)), no SP signal is detected at step S5, and thus after the SP signal detection timer times out (step S6), by way of precaution, it is checked whether or not the SC signal has been generated at step S12. In this case, since there is generated no SC signal as shown in FIG. 5(c), the PLL data of the succeeding channel is sent to the frequency synthesizer 24 at step S11, thereby the scanning is then shifted to the following channel.
As described above, in the prior art turbo scanning system, the SC signal detection waiting time period of 10 ms is extended to 100 ms only for the channel where the SP signal is generated or the SC signal is generated, provided that no SP signal has been generated within the SP signal detection waiting time period. On the other hand, if there is detected neither the SP signal during the SP signal detection waiting time period nor SC signal is detected, the channel scanning is shifted to the next channel substantially after the SP signal waiting time period has elapsed. Therefore, in a case where the SC signal is generated after the SP signal detection waiting time period has elapsed, it is not possible to stop searching, thus resulting in a failure in tuning.